1. Field of the Invention
This invention relates generally to the area of synchronizing to data transmissions received by a data receiver. Particularly this invention relates to a signal detector and bit synchronizer for use in a portable paging receiver.
2. Description of the Prior Art
Bit synchronization to a digital transmission is a process used to determine the presence of symbol boundaries of a data transmission and thereafter to provide a bit clock to synchronously sample data bits, or data symbols from the data transmission. Bit synchronization may be a process used in a paging receiver decoding a digital signaling protocol proposed by British Telecom in England which is commonly termed POCSAG (Post Office Code Standardization Advisory Group).
Synchronization to such a protocol is known and has been described in detail in U.S. Pat. No. 4,518,961, May 21, 1985, to Davis et al. which shows synchronization to either the POCSAG or a Golay signalling protocols. Additionally, U.S. Pat. No. 4,506,262, Mar. 19, 1985 to Vance et al. shows synchronization to POCSAG using an early/late phase locked loop with course and fine synchronization modes.
Line 10 of FIG. 1 shows a typical POCSAG signal. Prior to the signal, noise or another type of protocol may be transmitted as shown in area 12 enclosed in a broken line. The POCSAG signal begins with a preamble signal, 14, which consists of a number of one-zero transitions. The preamble is followed by a plurality of thirty two bit information words, each coded in a 31,21 extended BCH code (32,21). The information words begin with a sync code word 16a which contains predetermined binary sequence. Every seventeenth word thereafter another sync code, 16b, occurs in the signal. Between the sync codes, the information is structured as 8 information frames each of which contains two 32,21 words. For illustration, the contents of frame 4, as indicated by the number 18 in the figure, is shown on line 34. Line 34 has two 32 bit words, 36 and 38, each information word having 32 data bits structured in the 32,21 format. It can be appreciated that the data bits shown on line 34 can appear to be effectively a random sequence.
The sync code provides a means for frame synchronization to the signal. Thus it is desirable to first bit synchronize to the preamble signal and subsequently frame synchronize to the sync code. Line 20 shows the operation of a pager synchronizing to the POCSAG signal. During interval 22 and 24, the pager is attempting to synchronize to the signal. However, the signal is not present. During interval 26, the preamble signal, 14, is present, the pager bit synchronizes and finds sync code 16a. Then in a known manner, the pager decodes information in preassigned frame 4 as shown by intervals 28 and 32. The pager also tests for sync code 16b during interval 30 in order to determine the continued presence of the transmission.
In some instances, the preamble signal may be corrupted by noise rendering the the preamble signal undetectable. In this situation, it is desirable to acquire bit synchronization on the data bits within the thirty two bit words, and subsequently frame synchronize to one of the periodic sync code signals. The bit synchronization process in this mode is more difficult because the data in the thirty two bit words is effectively random. Consequently, it is desirable to provide a selective call receiver capable of acquiring bit synchronization on either a POCSAG preamble signal or data signals within POCSAG information words.
Battery life is a critical aspect of portable selective call receivers and it is desirable to conserve battery power whenever possible. In the absence of the POCSAG signal, selective call receivers operate in a low power mode and periodically activate receiving and decoding circuitry in order to detect the presence of the POCSAG signal. If no signal is detected, the paging receiver again operates in a low power mode. This process conserves battery power. Thus it is desirable to quickly detect the absence of the signal in order to hasten the return to the low power mode.
Consequently, it is desirable to provide a means for detecting the absence of the POCSAG signal in a minimal time, in doing so, additional battery power may be conserved. Prior art pagers have typically analyzed a predetermined number of transitions and in response to various algorithms determine the absence of the POCSAG signal. One such algorithm is shown in U.S. Pat. No. 4,554,665, Nov. 19, 1985 to Beesley. However, such using a predetermined number of transitions requires waiting for all of the transitions to occur. Such techniques suffer greatly under conditions where transitions occur relatively infrequently, such as when low frequency tones are transmitted in place of the POCSAG signal. While waiting for all of the transitions to occur the prior art receivers are consuming additional battery power. It is possible to anticipate whether the signal being received includes either the desired baud rate or not. If it is anticipated that the signal includes the desired baud rate it is desirable to configure a synchronizer to more rapidly detect the presence of the baud rate. While if it is anticipated that the signal does not include the desired baud rate, it is desirable to configure a synchronizer to rapidly detect the absence of the baud rate.
Furthermore, prior art paging receivers typically establish a predetermined relationship between the sensitivity of detecting the POCSAG signal in a noise environment and falsely detecting a POCSAG signal when only noise or another signal is present. Since upon the detection of the absence of a POCSAG signal, power is conserved by deactivating the receiver, this establishment results in a certain average battery power consumption while searching for signal. However because paging receivers are used in many different paging environments around the world, a sensitivity and falsing and battery power consumption performance in one application may not be optimal for another application. Thus it is desirable to construct a bit synchronizer for a paging receiver with easily variable sensitivity, falsing and power consumption characteristics.
Yet further, a new version of the POCSAG signal has a 1200 baud data rate. Typically bit synchronizers capable of synchronizing to a data transmission having random data at 1200 baud will also synchronize to data transmissions being an integer divisor of that data rate (600, 300 baud). However, the Golay Sequential Code (GSC) is another paging protocol which transmits message information at 600 and 300 baud. Thus it is desirable to positively and accurately detect the presence of 1200 baud data while being able to reject signals consisting only of a baud rate which is an integer divisor of 1200 baud.
Finally, in order to conserve power in a paging receiver having a microcomputer, it is desirable to provide a bit synchronizer capable of operating at a reduced microcomputer bus speed. Prior art paging receivers with microcomputers typically sample the incoming signal at a very high rate, and typically use a digital phase locked loop implemented in software in order to establish a bit clock for sampling data bits after synchronization. Software generated digital phase locked loops require high sampling rates and continuous phase adjustments in a real time software environment. This requires a microcomputer to operate at a relative high bus rate. U.S. Pat. No. 4,414,676, Nov. 8, 1983 to Kraul et. al. shows a synchronizer which in the preferred embodiment samples at five times the data rate and performs numerous calculations between each sample. Kraul et. al. does not show the capability to synchronize on random data. Thus it is desirable to construct a bit synchronizer which provides for a low sample rate. It is desirable to construct a bit synchronizer which in one operation establishes a bit clock synchronized to the data signal. These operations will provide for operating the microcomputer at a reduced bus rate thereby reducing the power consumption and extending the battery life of the paging receiver.